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Technology Information:


Structured ASIC - Disappearing from the Industry

By: Naor Mazza Reshef

In this article the Structured ASIC trend will be analyzied based on google web search tool google insight for search other trends like fpga and asic will be analyzed too.

What is stractured asic?

Stuctured asic is a concept of simplifying the development of asic. The asic device is construted of several layers which are costly to produce. Each layer requires a mask and an expensive production process. The concept of structured asic is to have a basic gate array of cells which will construct the bottom layers. only a few upper layers will be redesigned and manufactured. This cocept should reduce the costs and time to market.

This is the concept - it sounds promising, howevere the reality is completely different.

In the last decades many stuctured asic design centers has stopped their activity.

When the term "stuctured asic" is analyed with google insight for search tool - (a tool that analyzes volume of a search phrase), it shows that the search volume wss relativly high 5 years ago, however nowadys search volume is almost zero.

This sterngten the fact that many struture asic design centers were closed.

So were are we going? The optional technologies are asic and fpga. The fpga technology is more flexible - almost all layers are programmable. The disadvantage of fpga is capacity costs and speed. However with the evolving technology nowadays the gap is being closed.

So what are  the new trends - for medium small designs - fpga. For complex (e.g. with analog devices)  and large designs - Asic is the answer.

Application-Specific Integrated Circuit (ASIC)

Structured ASIC is an intermediate technology between ASIC and FPGA, offering high performance, a characteristic of ASIC, and low NRE cost, a characteristic of FPGA. Using Structured ASIC allows products to be introduced quickly to market, to have lower cost and to be designed with ease.

In a FPGA, interconnects and logic blocks are programmable after fabrication, offering high flexibility of design and ease of debugging in prototyping. However, the capability of FPGAs to implement large circuits is limited, in both size and speed, due to complexity in programmable routing, and significant space occupied by programming elements, e.g. SRAMs, MUXes. On the other hand, ASIC design flow is expensive. Every different design needs a complete different set of masks. The Structured ASIC is a solution between these two. It has basically the same structure as a FPGA, but being mask-programmable instead of field-programmable, by configuring one or several via layers between metal layers. Every SRAM configuration bit can be replaced by a choice of putting a via or not between metal contacts.

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